SystemVerilog Support in Vivado Simulator - 2024.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2024-05-30
Version
2024.1 English

The Vivado simulator supports the subset of SystemVerilog. The synthesizable set of SystemVerilog is listed in the following table. The supported test bench features are listed in Table 1.