The following table provides a quick reference and examples for common AMD Vivado™ simulator commands.
Parsing HDL Files | ||
Vivado simulator supports three HDL file types: Verilog, SystemVerilog and VHDL. You can parse the supported files using XVHDL and XVLOG commands. | ||
Parsing VHDL files |
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Parsing Verilog files |
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Parsing SystemVerilog files |
For information about the PRJ file format, see Project File (.prj) Syntax. |
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Additional xvlog and xvhdl Options | ||
xvlog and xvhdl Key Options |
See Table 1 for a complete list of command options. The following are key options for |
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Key Option | Applies to: | |
xelab, xvhdl, and xvlog xsim Command Options |
xvlog
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xelab, xvhdl, and xvlog xsim Command Options |
xvlog , xvhdl
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xelab, xvhdl, and xvlog xsim Command Options |
xvlog
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xelab, xvhdl, and xvlog xsim Command Options |
xvlog , xvhdl
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xelab, xvhdl, and xvlog xsim Command Options |
xvlog , xvhdl
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xelab, xvhdl, and xvlog xsim Command Options |
xvlog , xvhdl
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xelab, xvhdl, and xvlog xsim Command Options |
xvlog, xvhdl
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xelab, xvhdl, and xvlog xsim Command Options |
xvhdl, vlog
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xelab, xvhdl, and xvlog xsim Command Options |
xvlog , xvhdl
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Elaborating and Generating an Executable Snapshot | ||
After parsing, you can elaborate the design in
Vivado simulator using the
You can skip the parser stage, directly invoke the
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Usage |
xelab top1 top2
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Elaborates a design that has two top design units:
top1 and top2 . In this example, the design units are compiled in
the work library. |
xelab lib1.top1
lib2.top2
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Elaborates a design that has two top design units:
top1 and top2 . In this example, the design units have are compiled
in lib1 and lib2 , respectively |
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xelab top1 top2 -prj
files.prj
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Elaborates a design that has two top design units:
top1 and top2 . In this example, the design units are compiled in
the work library. The file
files.prj contains entries
such as:
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xelab top1 top2 -s
top
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Elaborates a design that has two top design units:
top1 and top2 . In this example, the design units are compiled in
the work library. After
compilation, xelab generates an
executable snapshot with the name top .
Without the -s top switch, xelab creates the snapshot by
concatenating the unit names. |
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Command Line Help and xelab Options |
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Running Simulation | ||
After parsing, elaboration and compilation stages are successful; xsim loads an executable snapshot to run simulation. | ||
Usage |
xsim top
-R
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Simulates the design to through completion. |
xsim top
-gui
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Opens the Vivado simulator workspace (GUI). | |
xsim top
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Opens the Vivado Design Suite command prompt in Tcl mode. From there,
you can invoke such options as:
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Important Shortcuts | ||
You can invoke the parsing, elaboration, and executable generation and simulation in one, two, or three stages. | ||
Three Stage |
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Two Stage |
where my_prj.prj file contains:
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Single Stage |
where my_prj.prj file contains:
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Note: If your design
contain UVM construct then you need to pass
-L uvm to xvlog and xelab command |
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Vivado Simulation Tcl Commands | ||
The following are commonly used Tcl commands. For a complete list, invoke following commands in the Tcl Console:
For information on any Tcl Command, type: |
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Common Vivado Simulator Tcl Commands: |
add_bp
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Add break point at a line of HDL source. |
add_force
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Force the value of a signal, wire, or register to a specified value. Tcl command exampled are provided on Using Force Commands. | |
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Report current simulation time. See Using a -tclbatch File for an example of this command within a Tcl script. | |
current_scope
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Report or set the current, working HDL scope. See Scope Window for more information. | |
get_objects
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Get a list of HDL objects in one or more HDL scopes, per the specified pattern. For example command usage refer to: Example SAIF Tcl Commands. | |
get_scopes
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Get a list of child HDL scopes. See Scope Window for more information. | |
get_value
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Get the current value of the selected HDL object
(variable, signal, wire, register). Type get_value -help in Tcl Console for more information.
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launch_simulation
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Launch simulation using the Vivado simulator. | |
remove_bps
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Remove breakpoints from a simulation. | |
report_drivers
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Print drivers along with current driving values for an HDL wire or signal object. Reference for more information: Using the report_drivers Tcl Command. | |
report_values
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Print current simulated value of given HDL objects (variables, signals, wires, or registers). | |
restart
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Rewind simulation to post loading state (as though the design was reloaded); time is set to 0. | |
set_value
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Set the HDL object (variable, signal, wire, or register) to a specified value. Reference for more information: Value Rules in Vivado Simulator Tcl Commands. | |
step
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Step simulation to the next statement. See Stepping Through a Simulation. |