You can perform functional or timing simulation after implementation. Timing simulation is the closest emulation to actually downloading a design to a device. It allows you to ensure that the implemented design meets functional and timing requirements and has the expected behavior in the device.
Important: Simulating timing
thoroughly prevents missed design defects, such as:
- The following post-synthesis and post-implementation
functionality changes caused by:
- Synthesis properties or constraints that create
mismatches (such as
full_caseandparallel_case) - UNISIM properties applied in the Xilinx Design Constraints (XDC) file
- The interpretation of language during simulation by different simulators
- Synthesis properties or constraints that create
mismatches (such as
- Dual port RAM collisions
- Missing, or improperly applied timing constraints
- Operation of asynchronous paths
- Functional issues due to optimization techniques
Note: For Versal
devices, post-synthesis and post-implementation simulation is supported only for fabric
logic (PL). Designs with Hard Blocks (NoC/AIE/PS) do not
support post-synthesis and post-implementation simulation. Designs using Hard Blocks
only support behavioral simulation.