Saving Simulation Results - 2024.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2024-05-30
Version
2024.1 English

The Vivado simulator saves the simulation results of the objects (VHDL signals, or Verilog reg or wire) being traced to the Waveform Database (WDB) file (<filename>.wdb) in the <project>.sim/<simset> directory.

If you add objects to the Wave window and run the simulation, the design hierarchy for the complete design and the transitions for the added objects are automatically saved to the WDB file. You can also add objects to the waveform database that are not displayed in the Wave window using the log_wave command. For information about the log_wave command, see Using the log_wave Tcl Command.