Most AMD IP deliver behavioral simulation
models for a single language only, effectively disabling simulation for language-locked
simulators if you are not licensed for the appropriate language. The simulator_language property ensures that an IP delivers a
simulation model for any given language. For example, if you are using a single language
simulator, you set the simulator_language property to
match the language of the simulator.
The Vivado Design Suite ensures the availability of a simulation model by using the available synthesis files of an IP to generate a language-specific structural simulation model on demand. For cases in which a behavioral model is missing or does not match the licensed simulation language, the Vivado tools automatically generate a structural simulation model to enable simulation. Otherwise, the existing behavioral simulation model for the IP is used. If no synthesis or simulation files exist, simulation is not supported.
simulator_language property cannot deliver a language-specific simulation netlist file if the generated Synthesized checkpoint (.dcp) is disabled.- In the Flow Navigator, click IP Catalog to open the IP catalog.
- Right-click the appropriate IP and select Customize IP from the popup menu.
- In the Customize IP dialog box, click OK.
The Generate Output Products dialog box (shown in the following figure) opens.
The following table illustrates the function of the simulator_language property.
| IP Delivered Simulation Model | simulator_language Value | Simulation Model Used |
|---|---|---|
| IP delivers VHDL and Verilog behavioral models | Mixed | Behavioral model (target_language) |
| Verilog | Verilog behavioral model | |
| VHDL | VHDL behavioral model | |
| IP delivers Verilog behavioral model only | Mixed | Verilog behavioral model |
| Verilog | Verilog behavioral model | |
| VHDL | VHDL simulation netlist generated from DCP | |
| IP delivers VHDL behavioral model only | Mixed | VHDL behavioral model |
| Verilog | Verilog simulation netlist generated from DCP | |
| VHDL | VHDL behavioral model | |
| IP delivers no behavioral models | Mixed, Verilog, VHDL | Netlist generated from DCP (target_language) |
|
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