Netlist Options - 2024.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2024-05-30
Version
2024.1 English

The Netlist tab provides access to netlist configuration options related to the SDF annotation of the Verilog netlist and the process corner captured by SDF delays. These options are stored as properties on the simulation fileset and are used while writing the netlist for simulation.