Use the SIMPRIM library for simulating timing simulation netlists produced after synthesis or implementation.
Important: Timing simulation is supported
only in Verilog; there is no VHDL version of the SIMPRIM library.
Tip: If you are a VHDL user, you can run post synthesis and
post implementation functional simulation (in which case no standard delay format (SDF)
annotation is required and the simulation netlist uses the UNISIM library). You can
create the netlist using the write_vhdl Tcl command. For usage information,
refer to the
Vivado
Design Suite Tcl Command Reference Guide (UG835).
Following is an example for specifying the library for Vivado simulator:
-L SIMPRIMS_VER
Where:
-
-L
is the library specification option. -
SIMPRIMS_VER
is the logical library name to which the Verilog SIMPRIM has been mapped.