Project File (.prj) Syntax - 2024.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2024-05-30
Version
2024.1 English
Note: The project file discussed here is a Vivado simulator text-based project file. It is not the same as the project file (.xpr) created by the Vivado Design Suite.

To parse design files using a project file, create a text file called <proj_name>.prj, and use the syntax shown below inside the project file.

verilog <work_library> <file_names>... [-d <macro>]...[-i <include_path>]... 
vhdl <work_library> <file_name>
sv <work_library> <file_name>
vhdl2008 <work_library> <file_name>

Where:

<work_library>: Is the library into which the HDL files on the given line are to be compiled.

<file_names>: Are Verilog source files. You can specify multiple Verilog files per line.

<file_name>: Is a VHDL source file; specify only one VHDL file per line.

  1. For Verilog or SystemVerilog: [-d <macro>] provides the option to define one or more macros.
  2. For Verilog or SystemVerilog: [-i <include_path>] provides the option to define one or more <include_path> directories.