Skipping Compilation - 2024.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2024-05-30
Version
2024.1 English

You can run the simulation on an existing snapshot and skip the compilation (or recompilation) of the design by setting the SKIP_COMPILATION property on the simulation fileset:

set_property SKIP_COMPILATION 1 [get_filesets sim_1]
Note: Any change to design files after the last compilation is not reflected in the simulation when you set this property.