Compiling Simulation Libraries Using Tcl Commands - 2024.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2024-05-30
Version
2024.1 English

Alternatively, you can compile simulation libraries using the compile_simlib Tcl command. For details, see compile_simlib in the Vivado Design Suite Tcl Command Reference Guide (UG835), or type compile_simlib -help.

Following are example commands for each third-party simulator:

Questa Advanced Simulator
Generating a simulation library for Questa for all languages and for all libraries and all families in the current directory.
compile_simlib -language all -simulator questa -library all -family all
ModelSim
Generating simulation library for ModelSim at /a/b/c, where the ModelSim executable path is <simulator_installation_path>.
compile_simlib -language all -dir {/a/b/c} -simulator modelsim -simulator_exec_path 
{<simulator_installation_path>} -library all -family all
VCS
Generating a simulation library for VCS for the Verilog language, for the UNISIM library at /a/b/c.
compile_simlib -language verilog -dir {/a/b/c} -simulator vcs -library unisim 
-family all
Xcelium
Generating a simulation library for Xcelium for the Verilog language, for the UNISIM library at /a/b/c.
compile_simlib -language verilog -dir {/a/b/c} -simulator xcelium -library unisim 
-family all