Re-running the Simulation After Design Changes (relaunch) - 2024.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2024-05-30
Version
2024.1 English

While debugging your HDL design with the Vivado simulator, you can determine that your HDL source code needs correction.

Use the following steps to modify your design and re-run the simulation:

  1. Use the Vivado code editor or other text editor to update and save any necessary source code changes.
  2. Use the Relaunch Simulation button on the Vivado IDE toolbar to re-compile and re-launch the simulation, as shown in the following figure. You might alternatively use the relaunch_sim Tcl command to re-compile and re-launch the simulation.
    Figure 1. Relaunch Simulation Button

  3. If the modified design fails to compile, an error box appears displaying the reason for failure. The Vivado IDE continues to display the results of the previous run of the simulation in a disabled state. Return to step 1 to correct the errors and re-launch the simulation again.

After the design successfully re-compiles, the simulation starts again.

Important: Relaunching might fail for reasons other than compilation errors, such as in the case of a file system error. If the Run buttons on the Simulation toolbar is grayed out after a re-launch, indicating that the simulation is disabled, check the contents of the Tcl Console for possible errors that have prevented the re-launch from succeeding.
CAUTION:
You might also re-launch the simulation using Run Simulation in the Flow Navigator or using launch_simulation Tcl command. However, using these options might fully close the simulation, discarding waveform changes and simulation settings such as radix customization.
Note: The Relaunch Simulation button is active only after one successful run of Vivado simulator using launch_simulation. The Relaunch Simulation button would be grayed out if the simulation is run in a Batch/Scripted mode.