To begin, analyze your HDL source files by type, as shown in the following table. Each command can take multiple files.
| File Type | Command |
|---|---|
| Verilog |
xvlog <VerilogFileName(s)>
|
| SystemVerilog |
xvlog -sv
<SystemVerlilogFileName(s)>
|
| VHDL |
xvhdl <VhdlFileName(s)>
|