When you run Post-Synthesis and Post-Implementation timing simulation, the simulators include:
- Gate-level netlist containing SIMPRIMS library components
- SECUREIP
- Standard Delay Format (SDF) files
You define the overall design functionality in the beginning. When the design is implemented, accurate timing information is available.
To create the netlist and SDF, the Vivado Design Suite:
- Calls the netlist writer,
write_verilog
with the-mode timesim
switch andwrite_sdf
(SDF annotator) - Sends the generated netlist to the target simulator
You control these options using Simulation Settings as described in Using Simulation Settings.
write_vhdl
Tcl command. For usage information, refer to the
Vivado
Design Suite Tcl Command Reference Guide (UG835).Post-Synthesis Timing Simulation
When synthesis runs successfully, the
option becomes available.After you select a post-synthesis timing simulation, the timing
netlist and the SDF file are generated. The netlist files include $sdf_annotate
command so that the generated SDF file is
picked up.
Post-Implementation Timing Simulations
When post-implementation is successful, the
option becomes available.After you select a post-implementation timing simulation, the timing
netlist and the SDF file are generated. The netlist files include $sdf_annotate
command so that the generated SDF file is
picked up.
Annotating the SDF File for Timing Simulation
When you specified simulation settings, you specified whether or not to create an SDF file and whether the process corner would be set to fast or slow.
Based on the specified process corner, the SDF file contains different
min
and max
numbers.
To run a hold check, create an SDF file with the -process_corner fast, and use the min column from the SDF file. The method for specifying which SDF delay field to use is dependent on the simulation tool you are using. Refer to the specific simulation tool documentation for information on how to set this option.
To get full coverage run all four timing simulations, specify as follows:
- Slow corner: SDFMIN and SDFMAX
- Fast corner: SDFMIN and SDFMAX
Running Standalone Timing Simulation
If you are running timing simulation from Vivado IDE, it adds the timing simulation-related switches to the simulator. If you run a standalone timing simulation, make sure to pass the following switch to simulators during elaboration:
For VCS:
+pulse_e/<number> and +pulse_r/<number> +transport_int_delays
During elaboration (with VCS)
For ModelSim/Questa Advanced Simulator:
+transport_int_delays +pulse_int_e/0 +pulse_int_r/0
During elaboration (with vsim)
-transport_int_delays -pulse_r 0 -pulse_int_r
0
. Table 1 provides descriptions for
these commands.