`uselib Verilog Directive - 2024.1 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2024-05-30
Version
2024.1 English

The Verilog `uselib directive is supported, and sets the library search order.

`uselib Syntax

<uselib compiler directive> ::= `uselib [<Verilog-XL uselib directives>|<lib 
directive>]
<Verilog-XL uselib directives> :== dir = <library_directory> | file = <library_file> 
| libext = <file_extension> 
<lib directive>::= <library reference> {<library reference>} 
<library reference> ::= lib = <logical library name>

`uselib Lib Semantics

The `uselib lib directive cannot be used with any of the Verilog-XL `uselib directives. For example, the following code is illegal:

`uselib dir=./ file=f.v lib=newlib 

Multiple libraries can be specified in one `uselib directive.

The order in which libraries are specified determines the search order. For example:

`uselib lib=mylib lib=yourlib 

Specifies that the search for an instantiated module is made in mylib first, followed by yourlib.

Like the directives, such as `uselib dir, `uselib file, and `uselib libext, the `uselib lib directive is persistent across HDL files in a given invocation of parsing and analyzing, just like an invocation of parsing is persistent. Unless another `uselib directive is encountered, a `uselib (including any Verilog XL `uselib) directive in the HDL source remains in effect. A `uselib without any argument removes the effect of any currently active `uselib <lib|file|dir|libext>.

The following module search mechanism is used for resolving an instantiated module or UDP by the Verific Verilog elaboration algorithm:

  • First, search for the instantiated module in the ordered list of logical libraries of the currently active `uselib lib (if any).
  • If not found, search for the instantiated module in the ordered list of libraries provided as search libraries in xelab command line.
  • If not found, search for the instantiated module in the library of the parent module. For example, if module A in library work instantiated module B of library mylib and B instantiated module C, then search for module C in the /mylib, library, which is the library of B (parent of C).
  • If not found, search for the instantiated module in the work library, which is one of the following:
    • The library into which HDL source is being compiled
    • The library explicitly set as work library
    • The default work library is named as work

`uselib Examples

Table 1. `uselib Examples
File half_adder.v compiled into Logical Library Named adder_lib File full_adder.v compiled into Logical Library Named Work
module half_adder(a,b,c,s); 
input a,b;
output c,s;
s = a ^ b;
c = a & b;
endmodule
module
full_adder(c_in, c_out, a, b, sum)
input c_in,a,b;
output c_out,sum;
wire carry1,carry2,sum1;
`uselib lib = adder_lib
half_adder
adder1(.a(a),.b(b),. c(carry1),.s(sum1)); half_adder adder1(.a(sum1),.b(c_in),.c (carry2),.s(sum)); c_out = carry1 | carry2; endmodule