The following table lists the supported port types.
VHDL 1 | Verilog/SV 2 |
---|---|
IN | INPUT |
OUT | OUTPUT |
INOUT | INOUT |
|
The following table shows the supported VHDL and Verilog data types for ports on the mixed language design boundary.
VHDL Port | Verilog Port |
---|---|
bit
|
net |
std_logic
|
net |
bit_vector
|
vector net |
signed
|
vector net |
unsigned
|
vector net |
std_ulogic_vector
|
vector net |
std_logic_vector
|
vector net |
Note: Verilog output port of type
reg
is supported on the mixed language boundary. On the boundary, an output reg
port is treated as if it were an output net (wire) port. Any other type found on mixed language boundary is considered an error.
Note: The Vivado simulator supports the record element as an actual in the port map of a Verilog module that is instantiated in the mixed domain. All those types that are supported as VHDL port (listed in Table 2) are also supported as a record element.
SV Data type | VHDL Data type |
---|---|
Int | |
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
byte |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
shortint |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
longint |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
integer |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
vector of bit(1D) |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
vector of logic(1D) |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
vector of reg(1D) |
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
|
logic/bit |
|
bit
|
|
std_logic
|
|
std_ulogic
|
|
bit_vector
|
|
std_logic_Vector
|
|
std_ulogic_vector
|
|
signed
|
|
unsigned
|
Note: VHDL entity instantiating Verilog
Module having a real port is supported.