Using Versal CIPS VIP - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
UG900
Release Date
2023-10-18
Version
2023.2 English

The AMD Versalâ„¢ adaptive SoC Control, Interfaces, and Processing System (CIPS) Verification Intellectual Property (VIP) supports the functional simulation of Versal adaptive SoC applications. It is targeted to enable the functional verification of the programmable logic (PL) by mimicking the processor system (PS)-PL interfaces and OCM memories of the PS logic. This VIP is delivered as a package of System Verilog modules. The VIP operation is controlled by using a sequence of System Verilog tasks. This is supported in the latest version of Vivado. For more information, see Versal Adaptive SoC CIPS Verification IP Data Sheet (DS996).