You are given the option in
Vivado®
IDE to
instantiate the XPLL in the core or the example design. This provides ease of use to
share the XPLL across multiple interfaces in a single bank. The core that has the XPLL
instantiated inside is called the master. Other instances of the wizard that do not have
the XPLL instance inside the core are called slaves.
The interface between the master and slave cores is shown in the following figure.
Note: When generating the master and
slave cores, the interface speed and other XPLL parameters should remain the same.
Both cores must reside within a single XPIO bank.
Since the wizard supports up to three banks, three XPLLs are instantiated in the
clk_scheme.v module. Based on the selection, the
clk_scheme.v signal is instantiated in the core or
example design.Figure 1. XPLL Sharing
A new GUI option (BANKS_IN_TRIPLET) has been added if more than one banks are selected to improve timing at XPHY level. A cascaded XPLL structure is implemented as shown in Figure 4 when the option is enabled. The clock output of master XPLL drives the clock input of slave XPLLs. ENABLE_PLL_CLKOUT1 option will be disabled when BANKS_IN_TRIPLET is turned ON.
If the number of banks is 3, XPLL1 is the master XPLL which drives the slave XPLL0 and XPLL2. If the number of banks is 2, XPLL1 is the master XPLL and the slave XPLL can be any one of the XPLLs.
Note: You should select optimum number of banks to avoid
over-usage of the XPLL instance and power.
Figure 2. XPLL sharing for multi bank design when BANKS_IN_TRIPLET is
Enabled
