Ports Connected to ACAP General Interconnect Logic - 1.0 English

Advanced IO Wizard LogiCORE IP Product Guide (PG320)
Document ID
PG320
Release Date
2022-10-19
Version
1.0 English
Table 1. Ports Connected to ACAP General Interconnect Logic
Port Direction Clock Domain Description
Data Ports
data_from_fabric_<sig_name> [sf*num_pins -1:0] Input app_clk Parallel data input from the interconnect logic to TX NIBBLESLICE. <sig_name> is the signal name configured for TX bus direction during customization. sf is the serialization factor. num_pins is the number of pins associated with the signal.
data_to_fabric_<sig_name>[sf*num_pins-1:0] Output app_clk Parallel data output to general interconnect logic from RX NIBBLESLICE. <sig_name> is the signal name configured for RX bus direction during customization. sf is the serialization factor. num_pins is the number of pins associated with the signal.
Clock Ports
fabric clk Output NA The frequency of this is data speed divided by the serialization factor. This is the master XPLL output clock which goes as input to the slave XPLL's. The clock can be used for general interconnect logic for bank 0 when BANKS_IN_TRIPLET is enabled.
div_clk1 Output NA The frequency of this can be set in Vivado IDE from a list of supported frequencies for the data speed chosen. This is the clk with deskew enabled. Enabled when BANKS_IN_TRIPLET =1
div_clk2 Output NA Frequency of XPLL_CLKOUT2 = data_speed/serialization factor. Serialization factor = the greater of TX and RX serialization factors. Enabled when BANKS_IN_TRIPLET = 1
pll_clkin Input NA Enabled when the Input Clock to XPLL is through a Clock capable pin and XPLL in Core option is chosen. Only one Input Clock pin needs to be chosen for entire multi bank interface for master XPLL. Enabled when BANKS_IN_TRIPLET = 1
pll_rst_in Input NA Reset Input to master XPLL. Enabled when BANKS_IN_TRIPLET = 1
bank<x>_pll_clkout0 Output NA The frequency of this is data speed divided by the serialization factor. This clock can be used as a clock for the general interconnect logic. x: bank number 0 to 2. Enabled when BANKS_IN_TRIPLET = 0
pll0_clkout0 Output NA The frequency of this is data speed divided by the serialization factor. This clock can be used as a clock for the general interconnect logic. x: bank number 0 to 2. Enabled when BANKS_IN_TRIPLET = 0
bank<x>_pll_clkin Input NA Enabled when the Input Clock to XPLL is through a Clock capable pin and XPLL in Core option is chosen. Only one Input Clock pin needs to be chosen for the entire multi bank interface x: bank number 0 to 2. Enabled when BANKS_IN_TRIPLET = 0
bank<x>_pll_rst_pll Input NA Reset input to XPLL x: bank number 0 to 2. Enabled when BANKS_IN_TRIPLET = 0
bank<x>pll_clkout1 Output NA The frequency of this can be set in Vivado IDE from a list of supported frequencies for the data speed chosen. x: bank number 0 to 2. Enabled when BANKS_IN_TRIPLET = 0 and ENABLE_PLLOUT1 = 1
bank<x>_pll_clkout2 Output NA Frequency of XPLL_CLKOUT2 = data_speed/serialization factor. Serialization factor = the greater of TX and RX serialization factors x: bank number 0 to 2. Enabled when BANKS_IN_TRIPLET = 0
bank<x>_pll_clkout3 Output NA Frequency of XPLL_CLKOUT3 = data_speed/serialization factor. Serialization factor = the lesser of TX and RX serialization factors x: bank number 0 to 2. Enabled when BANKS_IN_TRIPLET = 0
bank<x>_pll_clkoutphy Output Not applicable This port is available when you choose to instantiate the XPLL in the core. The pll_clkoutphy signal from the master core is the output to the slave core. x: bank number 0 to 2. For more information, see Clocking section. Enabled when BANKS_IN_TRIPLET = 0
RIU Ports
riu_addr Input ctrl_clk Address of the RIU register. Width of this bus is [num_banks*72-1:0] when SIMPLE_RIU parameter is disabled. When this parameter is enabled the width is [7:0]
ctrl_clk Input NA System clock from the general interconnect. CTRL_CLK must be free running.
riu_nibble_sel[num_banks*8:0] Input ctrl_clk Width of this bus is [num_banks*9-1:0] when SIMPLE_RIU parameter is disabled. Each bit in the riu_nibble_sel corespondent to each nibble in the bank. Enable the bits to use the RIU Interface of particular nibble. To broadcast the writes, all bits can be set to "1".
riu_wr_data[num_banks*144-1:0] Input ctrl_clk Input write data to the register. Width of this bus is [num_banks*144-1:0] when SIMPLE_RIU parameter is disabled. When this parameter is enabled width is [15:0]
riu_wr_en Input ctrl_clk Register write enable active-High. Width of this bus is [num_banks*9-1:0] when SIMPLE_RIU parameter is disabled. When this parameter is enabled width is 1
riu_rd_data[num_banks*144-1:0] Output ctrl_clk Output read data to the controller .Width of this bus is [num_banks*144-1:0] when SIMPLE_RIU parameter is disabled. When this parameter is enabled width is [15:0]
riu_rd_valid[num_banks*8:0] Output ctrl_clk Output read valid to the controller .Width of this bus is [num_banks*9-1:0] when SIMPLE_RIU parameter is disabled. When this parameter is enabled width is 1 There can be a possibility of collision between BISC and PL where valid plays a crucial role in determining the validity of RIU.
Note: RIU ports are available only when ENABLE_RIU_INTERFACE parameter is selected.
riu_sm_done Output ctrl_clk Indication of RIU state machine done. This is exposed in the IP only when you select Enable BIDIR State Machine option from the GUI or EN_BIDIR_SM =1. The option of EN_BIDIR_SM is available only in the case of BIDIR or BIDIR mix modes.
Status/Control
bank<x>_pll_locked Output NA Logic High indicates XPLL is locked to the desired clock frequency. x: indicates the bank number 0 to 2.
en_vtc Input ctrl_clk Assert to enable VTC for all interfaces.
intf_rdy Output ctrl_clk It indicates that the reset sequence of the interface is done.
rxtx_cntvaluein_<<port_name>> Input ctrl_clk This port would be enabled when delay control ports or enable all ports parameters are enabled. Width would be 9*bus width. Refer to Versal ACAP SelectIO Resources Architecture Manual (AM010) for more details on the port.
rxtx_cntvalueout_<<port_name>> Output ctrl_clk This port would be enabled when delay control ports or enable all ports parameters are enabled. Width would be 9*buswidth. Refer to Versal ACAP SelectIO Resources Architecture Manual (AM010) for more details on the port.
rxtx_ce_<<port_name>> Input ctrl_clk This port would be enabled when delay control ports or enable all ports parameters are enabled. Refer to Versal ACAP SelectIO Resources Architecture Manual (AM010) for more details on the port.
rxtx_inc_<<port_name>> Input ctrl_clk
rxtx_ld_<<port_name>> Input ctrl_clk
rxtx_sel _<<port_name>> Input ctrl_clk
rxen_vtc_<<port_name>> Input ctrl_clk
txen_vtc_<<port_name>> Input ctrl_clk
fifo_empty [num_banks*9-1 :0] Output app_clk Aggregated FIFO empty flag from each nibble which contains RX/TX/BiDir Pins.
Note: Do not rely on FIFO_EMPTY asserting every eight FIFO_WR_CLK cycles for bit and word alignment. The first deassertion of FIFO_EMPTY must be used for controlling FIFO_RDEN.
Note: The width of the port is 27 by default. When REDUCE_CONTROL_SIG_EN parameter is enabled, the port width is reduced to 1. All ports together give a single bit output using the "OR" operation. This feature reduces the number of ports exposed to the customers.
fifo_rd_en [num_banks*9-1 :0] Input app_clk FIFO read enable for each bit slice. <i> is the pin number on which the RX is selected.
Note: The width of the port is 27 by default. When REDUCE_CONTROL_SIG_EN parameter is enabled, the port width is reduced to 1. All ports together give a single bit output using the "OR" operation. This feature reduces the number of ports exposed to the customers.
fifo_rd_clk Input app_clk FIFO read clock for the interface.
fifo_wr_clk Output fifo_wr_clk FIFO write clock for the interface. Select PLL_FIFO_WRITE_CLK_EN parameter to enable this clock.
start_bitslip Input Not applicable Reset for the bitslip logic. Active-Low. When the top level reset pin is asserted, start_bitslip should be driven Low. The start_bitslip port should be deasserted only when the Transmit partner of the serial line is transmitting the bitslip training pattern.
bitslip_error_<sig_name> [num_pins-1 :0] Output fifo_rd_clk Error output for bitslip. When eight bitslips are performed for 8-bit serialization or four bitslips are performed for 4-bit serialization, this output is pulsed high.
bitslip_sync_done Output fifo_rd_clk Indicates that the bitslip training pattern is received at all RX pins in the design.
shared_bank<x>_pll_clkoutphy_in Input Not applicable This port is available when you choose to instantiate the XPLL in the example design. The pll_clkoutphy signal from the master core is given as an input to the slave core.
shared_bank<x>_pll_locked_in Input Not applicable This port is available when you choose to instantiate the XPLL in the example design. The pll_locked signal from the master core is given as an input to the slave core.
shared_bank<x>_pll_clkoutphyen_out Output Not applicable This port is available when you choose not to instantiate the XPLL in the core. The pll_clkoutphy_en signal from the slave core is given as an input to the master core.
tx_app_clk Input Not Applicable This is the clock used to drive the fabric side ports related to TX pins. Available for asynchronous applications.
rx_app_clk Input Not Applicable This is the clock used to drive the fabric side ports related to RX pins. Available for asynchronous applications.
gearbox_clk Input Not Applicable This clock drives gearbox for asynchronous interfaces.
parallel_clk Input Not Applicable This port is available when PLL in outside core and Enable BLI is true. This is the clock on which user sends the data_from_fabric. Advanced IO Wizard needs this clock to synchronize the data_from_fabric and place n BLI for timing closure.
dly_rdy [num_banks*9-1 :0] Output Async dly_rdy from XPHY is given as output. Indicates that delay line values can be changed
Note: The width of the port is 27 by default. When REDUCE_CONTROL_SIG_EN parameter is enabled, the port width is reduced to 1. All ports together give a single bit output using the "OR" operation. This feature reduces the number of ports exposed to the customers.
phy_rdy [num_banks*9-1 :0] Output Async phy_rdy from XPHY is given as output. Indicates that the PHY is ready for voltage and temperature compensation (VTC)
Note: The width of the port is 27 by default. When REDUCE_CONTROL_SIG_EN parameter is enabled, the port width is reduced to 1. All ports together give a single bit output using the "OR" operation. This feature reduces the number of ports exposed to the customers.
phy_rden [num_banks*36-1 :0] Input app_clk This port is input to XPHY. Port width is 36 * <number of banks>. These are nibble-level pins. Each nibble instantiated contributes to four pins. Used to control the gate on the receiver.
Note: Refer to Versal ACAP SelectIO Resources Architecture Manual (AM010) to understand how phy_rden is set up to control the RX datapath. The wizard places and routes PHY_RDEN[3,1] when RX_DATA_WIDTH is 4, even though they are unused. PHY_RDEN[3,1] can be ignored when RX_DATA_WIDTH is 4 for timing analysis.
phy_wren [num_banks*36-1 :0] Input app_clk This port is input to XPHY. Port width is 36 * <number of banks>. These are nibble-level pins. Each nibble instantiated contributes to four pins. It is used to control the gate on the transmitter, and can also be used to control tristating when it is set to serialized.
Note: Refer to Versal ACAP SelectIO Resources Architecture Manual (AM010) to understand how phy_wren is set up to control the TX datapath. The wizard places and routes PHY_WREN[3,1] when TX_DATA_WIDTH is 4, even though they are unused. PHY_WREN[3,1] can be ignored when TX_DATA_WIDTH is 4 for timing analysis.
phy_rdcs0 [num_banks*36-1 :0] Input app_clk This port would be available when ENABLE_ALL_PORTS parameter is enabled.
phy_rdcs1[num_banks*36-1 :0] Input app_clk This port would be available when ENABLE_ALL_PORTS parameter is enabled.
phy_wrcs0[num_banks*36-1 :0] Input app_clk This port would be available when ENABLE_ALL_PORTS parameter is enabled.
phy_wrcs1[num_banks*36-1 :0] Input app_clk This port would be available when ENABLE_ALL_PORTS parameter is enabled.
gt_status[num_banks*9-1 :0] Output Async This port would be available when ENABLE_ALL_PORTS parameter is enabled.
VREF_ID Input NA This port has a length of 4 bits. Because there are nine nibbles in a bank, the valid values of VREF_ID are 0 to 8. For example, for nibble 5, the VREF_ID must be 4’h5. To broadcast it, set VREF_ID to 0xF.
fabric_VREF_TUNE Input NA This port has a 10-bit value. This must be enabled per each bank.
  1. For more details on ports related to XPHY, refer to the XPHY Primitive Ports section in the Versal ACAP SelectIO Resources Architecture Manual (AM010).