| Global
Ports |
| <input_clock_name> |
Input |
NA |
Differential/Single Ended clock input connected to
XPLL. The port is available only when an XPLL is instantiated in the core. |
| rst |
Input |
ctrl_clk |
Global reset pin. CTRL_CLK Free Running Requiremetn, assertion
of the reset is asynchronous. De-assertion is synchronous with respect to the
CTRL_CLK. Minimum pulse width should be 5 ns. |
| <port_name> |
Input/Output/Inout |
NA |
Data/Input Clock/Strobe/Clk forward/WrClk/RdClk ports connected
to I/O pins. Port name of the wizard IP is user-specified through the
Vivado®
Integrated Design Environment (IDE). |