FIFO Modes - 1.0 English

Advanced IO Wizard LogiCORE IP Product Guide (PG320)

Document ID
PG320
Release Date
2022-10-19
Version
1.0 English

A new option is added to the GUI called FIFO_MODES to select different modes supported by XPHY. This feature is currently in beta mode. Following are the different FIFO modes:

Sync Mode
In this mode, FIFO_RD_CLK and FIFO_WR_CLK are equal. FIFO_RD_CLK must be driven by a BUFG connected to FIFO_WR_CLK. FIFO_RD_EN is controlled by a new parameter called FIFO read enable control that connects the FIFO_RD_EN signal to the inverse of FIFO_EMPTY.
Async Mode
It is a default FIFO mode with FIFO_RD_CLK and FIFO_WR_CLK.
Bypass Mode
In this mode, FIFO_WR_CLK is the output from XPHY. FIFO_RD_CLK, FIFO_RD_EN, and FIFO_EMPTY are masked at bank wrapper level. FIFO_RD_EN is connected to logic low level and FIFO_EMPTY is connected to logic high level.
Figure 1. FIFO Modes

Following are the user parameters of the FIFO mode:

Table 1. User Parameters Specific to this Feature
Parameter Range Default Value
FIFO_MODE_GUI_EN

False

True

False
FIFO_MODES

SYNC

ASYNC

BYPASS

ASYNC
FIFO_RD_EN_CONTROL

False

True

False