IO Timing Estimation Tab - 1.0 English

Advanced IO Wizard LogiCORE IP Product Guide (PG320)

Document ID
PG320
Release Date
2022-10-19
Version
1.0 English

IO Timing Estimation tab provides IO related timing estimation with respect to the user inputs given in previous tabs. IO Timing Estimation tab is shown in the following figure:

Figure 1. IO Timing Estimation Tab

The Advanced IO Wizard adds a new tab to estimate the error associated with the XPHY, I/O, and relevant clocking resources in source synchronous designs.

  • BIT Period

    This parameter is derived based on the interface speed mentioned in the Basic tab.

  • TX/RX IOB – Error from input and output buffers.

    For receiver designs, I/O settings affect the error. For example, single-ended IOSTANDARDs require the VREF to be properly set whereas differential inputs are not susceptible to the same types of tuning. The timing budget accounts for internal VREF tuning. Nominal VID swings are assumed for differential inputs.

    For transmitters, single ended I/O’s can have higher duty-cycle distortion than differential standards. Takes into account VCC induced jitter.

  • TX/RX PHY – Error from XPHY

    For receivers within source synchronous designs, the XPHY uses the strobe (DQS from XCC pins) as the capture clock. As a result, clock noise is only based on the XPHY clocking structures. The reference clock (XPHY’s PLL_CLK) only affects the tuning associated with BISC.

    For asynchronous, receive designs that use SERIAL_MODE with PLL_CLK as the clock source, an alignment circuitry must be used. The error associated with dynamic phase alignment circuitry is not covered.

    PHY accounts for all receiver errors within XPHY that are not tuned out by BISC. BISC adjusts for center aligned and edge aligned data for a single bank by adjusting input delays (ALIGN_DELAY) and strobe delays.

    For transmitters, XPHY always uses PLL_CLK as the clock source for the transmitted data. As a result, noise associated with the XPLL must be accounted for. TX_OUTPUT_PHASE_90 affects the noise associated with the XPLL.

    For the transmitter, BISC is limited to the tuning of DELAY_VALUE to tune the output delays to the supplied PLL_CLK and REFCLK_FREQUENCY settings.

  • Package

    During the start up sequence when BISC is performed, XPHY sends the routing used by the strobe to deskew the nibbleslices. The strobe routing is deskewed for all on-die variations after BISC is done.

    Please note that the package skews are not part of the BISC calibration scheme. Package skews can be matched by PCB skews. For any unmatched package skews, the timing budget must add those skews separately to the timing budget.

    Package delays are reported in the Package Pins tab of an implemented design or by using the File > Export > “Export I/O Ports…” menu.

  • Channel

    High speed interfaces require good PCB design practices and signal integrity. As a result, PCB design choices and I/O settings can impact the performance. IBIS simulations are typically used to simulate the signal integrity associated with PCB and I/O settings. Any IOSTANDARD, SLEW, PREEMPHASIS, termination decisions should be simulated to determine the channel loss. Channel loss should also be included into the final timing budget to determine the receiver and transmitter margins.

  • Total Window Opening Remaining in TX/RX

    This is calculated by removing all the calculated delays from the available Bit Period.