User Parameters - 1.0 English - PG320

Advanced IO Wizard LogiCORE IP Product Guide (PG320)
Document ID
PG320
Release Date
2025-03-19
Version
1.0 English

The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).

Table 1. User Parameters
Vivado IDE Parameter User Parameter Default Value

Bus Direction

  • TX_ONLY: 0
  • RX_ONLY: 1
  • BiDir: 2
  • TX+RX: 3
  • BiDir+TX+RX: 4
 BUS_DIR 0
BiDir Mode
  • Independent WrClk and RdClk:0
  • Single Continuous Clock: 1
  • Single Strobe: 2
 BIDIR_MODE 1
Enable BIDIR state machine
Range:
  • FALSE: 0
  • TRUE: 1
Note: This option is available only in the case of BIDIR or Mix of BIDIR modes.
 EN_BIDIR_SM 0

Interface Speed (Mb/s)

Range: 200-1800 Mb/s

Note: The range is subjected to change based on below selections:
  1. Source Sync or Async.
  2. Speed grade of the device selected.
 DATA_SPEED 1000

PLL Clk Input Frequency (MHz)

Range: 100-1099 MHz

Note: The rage is subjected to change based on the speed grade selected
 INPUT_CLK_FREQ 500.00

Clock to Data Relation (RX Strobe)

Range:

  • ASYNC/NONE: 2
  • Center DDR: 3
  • Edge DDR: 4
 CLK_TO_DATA_ALIGN 4

PLL Clock Source

Range:

  • Clock Capable Pin: IBUF_TO_PLL
  • Fabric (Driven by BUFG): BUFG_TO_PLL
 PLL_CLK_SOURCE BUFG_TO_PLL

Enable Custom CDR

Range:

  • False : 0
  • True : 1
 ENABLE_CUSTOM_CDR 0

TX, RX Serialization Factor

Range: 2,4,8

 TX/RX_SERIALIZATION_FACTOR 8

Serialization Factor

Range: 2,4,8

 SERIALIZATION_FACTOR 8

Select if PLL is included in core or Example Design

Range:

  • Include PLL in Core: 0
  • Include PLL in Example Design: 1
 PLL_IN_CORE 0

Forwarded Clock Phase (TX Signal Type = Clk Fwd)

Range:

  • FALSE: 0
  • TRUE: 1
 CLK_FWD_PHASE 0

Single Ended IO Standard

Range:

Varies with device

 SINGLE_IO_STD NONE

Differential IO Standard

Range: Varies with device

 DIFFERENTIAL_IO_STD NONE

RIU Interface

Range:

  • FALSE: 0
  • TRUE: 1
 ENABLE_RIU_INTERFACE 0

Enable Simple RIU

Range:

  • FALSE: 0
  • TRUE: 1
 SIMPLE_RIU 0

Enable BitSlip

Range:

  • FALSE: 0
  • TRUE: 1
 ENABLE_BITSLIP 0

Enable Data Bitslip

Range:

  • False: 0
  • True: 1
 ENABLE_DATA_BITSLIP 0

3-state

  • Serialized: 0
  • Combinatorial: 1
 DATA_TRISTATE 1
Number of Channels BUS<0-16>_NUM_PINS 1
Signal Name BUS<0-16>_SIG_NAME Data_pins_0

Pin Direction

  • None: None
  • RX: RX
  • TX: TX
  • BiDir: BiDir
 BUS<0-16>_DIR None

Signal IO Type

  • Differential: DIFF
  • Single-ended: SINGLE
 BUS<0-16>_IO_TYPE SINGLE
Signal Type BUS<0-16>_SIG_TYPE Data
Enable Strobe BUS<0-16>_STROBE_EN False
Strobe Name BUS<0-16>_STROBE_NAME Strobe_0
Enable WrClk BUS<0-16>_WRCLK_EN False
WrClk Name BUS<0-16>_WRCLK_NAME WrClk_0

Strobe IO Type

  • Differential: DIFF
  • Single-ended: SINGLE
 BUS<0-16>_STROBE_IO_TYPE SINGLE

WrClk IO Type

  • Differential: DIFF
  • Single-ended: SINGLE
 BUS<0-16>_WRCLK_IO_TYPE SINGLE

Application Data Width

Range: 4 and 8

 APPLICATION_DATA_WIDTH 8

Application

Range:

  • SOURCE_SYNCHRONOUS
  • ASYNCHRONOUS
 APPLICATION_TYPE SOURCE_SYNCHRONOUS

FIFO_WRCLK_OUT

Range:

  • False: 0
  • True: 1
 PLL_FIFO_WRITE_CLK_EN False

Reduce Control Signal

Range:

  • False: 0
  • True: 1
 REDUCE_CONTROL_SIG_EN False

IOB Power saving

Range:

  • False: 0
  • True: 1
 ENABLE_IOB_POWER_SAVING Fallse
IOB Power control

Range:

  • User Controlled: 0
  • Wizard Controlled: 1
 IOB_POWER_CONTROL User Controlled
Enable Delay Control Signals

Range:

  • False: 0
  • True: 1
 DELAY_CTRL_SIG_EN False
ENABLE CDR DEBUG SIGNALS

Range:

  • False: 0
  • True: 1
 ENABLE_CDR_DEBUG False
Enable BLI Logic

Range:

  • False: 0
  • True: 1
 ENABLE_BLI True
Enable Debug Ports

Range:

  • False: 0
  • True: 1
 ENBALE_DEBUG_PORTS False
Enable ILA in Example Design

Range:

  • False: 0
  • True: 1
 ENABLE_ILA_IN_EXDES False
Multi Banks are Part of a Triplet

Range:

  • False: 0
  • True: 1
 BANKS_IN_TRIPLET False

FIFO mode enablement

Range:

  • False: 0
  • True: 1
 FIFO_MODE_EN_GUI False

FIFO mode options

Range:

  • SYNC
  • ASYNC
  • BYPASS
 FIFO_MODES ASYNC

FIFO read enable user control

Range:

  • False: 0
  • True: 1
 FIFO_RD_EN_CTRL False
Strobe Selection (For PLL input)

Range:

  • Bus0_Strobe : 0
  • Bus1_Strobe : 1
  • Bus2_Strobe : 2
  • Bus3_Strobe : 3
  • Bus4_Strobe : 4
  • Bus5_Strobe : 5
  • Bus6_Strobe : 6
  • Bus7_Strobe : 7
  • Bus8_Strobe : 8
  • Bus9_Strobe : 9
  • Bus10_Strobe : 10
  • Bus11_Strobe : 11
  • Bus12_Strobe : 12
  • Bus13_Strobe : 13
  • Bus14_Strobe : 14
  • Bus15_Strobe : 15
 STROBE_SEL 0
PACKAGE PACKAGE 0.0
CHANNEL CHANNEL 0.0
  1. Parameter values are listed in the table where the Vivado IDE parameter value differs from the user parameter value. Such values are shown in this table as indented below the associated parameter.