The functional block diagram of the core is shown in the following figure.
Figure 1.
Core Block
Diagram
Note: PLL0, PLL1, PLL2 are the XPLL blocks.
Each I/O bank in Versal® devices contains 54 pins (9 nibbles) that can be used for input and output. The Advanced IO Wizard provides various options to generate a wrapper using XPHY primitive for the user selected configuration of the XPHY features of high performance banks. This wizard also configures clocking circuitry using XPLL that is needed to support these configurations. The reset and initialization sequence is also provided in the HDL wrapper.