When you turn around the bus, you are adding some commands to make sure that the interface and the RX gating is properly reset.
Note: PHY_WREN and PHY_RDEN have
a latency of 3 clock cycles, they have synchronizes added to take care of cross clock
domain.
Note: The turn around time in
BIDIR mode must be handled by the user, as the XPHY needs specific time for the
transition between TX and RX. In the example design, it is handled in simple case by
providing some time gap in the conversion.