Versal Architecture I/O Planning Design Flow Changes - 1.0 English

The Vivado® Design Suite has the following differences between the I/O assignment and implementation process for the Versal architecture Advanced IO Wizard:

• Consolidated I/O Planning with the rest of the design in the main Vivado IDE I/O Planning view layout—this enables pin planning with the design RTL or after synthesizing the design. Additionally, you can pin plan all the high speed I/Os in a bank together including hard and soft memory controllers.
• PHY implementation of the IP is now performed after synthesis as a part of the opt_design command, this enables netlist based I/O planning.
• Physical block (Pblock) that contains the IP is now automatically generated as a part of the opt_design command and is transient and invisible to users.