CTRL clock is mandatory for a design. The reset state machine and XPHY nibble
modules operate on the CTRL clock. It can be provided through the ctrl_clk input port. This clock can be sourced from a valid clock source
that is internal or external to the ACAP. clkout1 output of PLL can be used as ctrl_clk. Use ENABLE_PLLCLKOUT1 parameter to enable this
clock.