Required Constraints
This section is not applicable for this IP core.
Device, Package, and Speed Grade Selections
Input clock frequency selection depends on the maximum frequencies supported by IBUF/BUFG. Select the device, package and speed grades after referring to the Versal Architecture and Product Data Sheet: Overview (DS950) for details on supported maximum frequencies.
Clock Management
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.