Clocking of RX - 1.0 English

There are two modes used to capture data in the XPHY initiated by an attribute (SERIAL_MODE = TRUE/FALSE).

• When the attribute SERIAL_MODE is set to TRUE, the received data is captured using CLKOUTPHY from XPLL. This corresponds to the asynchronous option shown in Vivado IDE for clock to data alignment. The receive data capture clock and receive data are either asynchronous or synchronous phase unknown. These types of applications require specialized extra logic designs to handle data recovery which is called CDR logic. The CDR logic needed for data capture is built into the wizard.