Use SERIAL_MODE = TRUE/FALSE to capture data in the XPHY initiated by an attribute.
When the attribute SERIAL_MODE
is set to TRUE, the received data is captured using
CLKOUTPHY from XPLL. This corresponds to the
asynchronous option shown in Vivado IDE for clock to
data alignment. The receive data is either asynchronous or synchronous phase unknown.
These types of applications require specialized extra logic designs to handle data
recovery, known as CDR logic. The CDR logic needed for data capture is built into the
wizard. For applications where the CDR circuitry is created by external fabric logic,
the wizard alternatively provides a custom CDR setting so that you can create your own
CDR logic.
When the attribute SERIAL_MODE is set to FALSE, the
received data is captured by Strobe/RdClk. The Strobe/RdClk is a dedicated clock used by
XPHY for capturing receive data. This Strobe/RdClk is separate from the PLL clock input.
Strobe typically implies a clock that can be stopped, and RdClk or capture clock is for
free running clocks. For applications where word alignment is needed, the starting of
the Strobe/RdClk determines the start of the capturing of receive data that can define
the word alignment.
The Strobe/RdClk uses the dedicated clock routing internal to the XPHY logic. These inter-nibble and inter-byte clock routes are limited to a single bank. For applications where multi-bank has been selected, a Strobe/RdClk is required for each bank. A three bank interface therefore requires at least three Strobe/RdClks.
To combine the PLL input clock and Strobe/RdClk into a single pin, set PLL Clock Source to Clock Capable Pin and PLL Driven by Data Capture Clock to Yes. When the Strobe/RdClk is also the PLL input clock, the input frequency is restricted to the frequency needed for the interface speed (or interface speed / 2). In using this mode, because the Strobe/RdClk is free running, bitslip is needed to address word alignment.
The Strobe/RdClk is used to directly capture the incoming data. The Clock Data Relation (RX Strobe) setting determines if the Strobe/RdClk is edge aligned or center aligned.