The wizard generates a reset module that is built in the wrapper. This module
runs on the Ctrl clock. The input is an asynchronous reset that triggers
resets to all XPHY modules in the design.
When any pin is enabled as Clock Forward, it
is mandatory to hold the counterpart design (RX) in reset until the TX is out of reset and
intf_rdy of TX is asserted. This ensures a reliable clock to the RX.