Data is transmitted on the serial lines along with the associated clock or
strobe. The clock forwarding option in the wizard can be enabled on any pin in a given
bank. It is mandatory that the number of Clock Forward
pins are less than or equal to the number of TX pins in the design. To configure the
phase of the forwarded clock with respect to the data, set Forwarded Clock Phase (Tx Signal Type = Clk Fwd) to 0 for edge-aligned
interfaces and 90 for center-aligned interfaces. The Clock
Forward pin acts as a clock/strobe for RX. The clock/strobe can be
edge-aligned or center-aligned with the data. Clock/strobe is generated similar to the
data by applying a 01010101 pattern at the D[7:0] input of XPHY nibble. Alignment can be
determined on the TX or RX side from an XPHY perspective (TX_OUTPUT_PHASE_# vs
RX_CLK_PHASE_P/N).
Note: For TX only applications, a forwarded clock is not required for
the core to be generated. For interfaces without a forwarded clock, the example design
is supported. The example designs for TX interfaces are based on source synchronous
applications that require a forwarded clock.