Create and Configure the Advanced IO Wizard - 1.0 English

Next, create and configure the Advanced IO Wizard IP for the 12-bit DDR source-sync receive interface.

1. In the block design canvas, click Add IP.
2. In the popup, search for Advanced IO Wizard and double-click Advanced IO Wizard to add it to the canvas.
   
3. On the canvas, double-click Advanced IO Wizard IP to step through IP configuration:
   1. In the Basic tab under Clocking, set:
      • Interface Speed: 600.00
      • PLL Input Clock Frequency: 300.00
   2. In the Advanced tab under IO Standard Selection, set:
      • Single IO Std: SSTL12
   3. In the Pin Configuration tab, specify the receive interface as follows:
      • Pin Direction: RX
      • IO Type: Single-ended
      • Signal Type: Data
      • Enable Strobe: click to select
      • Strobe/RdClk Name: strbClk
      • Signal Name: dataIn
      • Number of Data Channels: 12
      
   4. Skip the IO Timing Estimation tab for this tutorial.

The Tcl commands used to create and configure the receive interface are as follows:

create_bd_cell -type ip -vlnv xilinx.com:ip:advanced_io_wizard:1.0 \
                              advanced_io_wizard_0

set_property -dict [list CONFIG.DATA_SPEED {600.00} \
                         CONFIG.INPUT_CLK_FREQ {300.000} \
                         CONFIG.BIT_PERIOD {1667}] \
                         [get_bd_cells advanced_io_wizard_0]

set_property -dict [list CONFIG.DIFF_IO_STD {NONE} \
                         CONFIG.SINGLE_IO_STD {SSTL12}] \
                         [get_bd_cells advanced_io_wizard_0]

set_property -dict [list CONFIG.BUS0_NUM_PINS {12} \
                         CONFIG.BUS0_STROBE_NAME {strbClk} \
                         CONFIG.BUS0_SIG_NAME {dataIn}] \
                         [get_bd_cells advanced_io_wizard_0]