The Versal® architecture Advanced IO Wizard IP defines various IO configurations using a pre-engineered application layer and a physical layer (XPHY). External high speed interfaces must follow the following rules:
- Specific pinout requirements driven by clocking
- Rule based engine for I/O configuration within the I/O banks
- Physical pin assignment requirements
For performance purposes, the final configuration of the IP is dependent on the I/O assignments. Therefore, you cannot complete final implementation of the IP until the IP I/O is assigned. You must handle the I/O assignment and implementation of this IP differently from most other IPs. However, this is similar to how memory IP does pin placement. This section describes the process for I/O planning and implementation of the Versal Advanced IO Wizard IP.