Advanced Bit Mode - 1.0 English

Advanced bit mode allows you to override the XPHY attributes at XPHY level. Currently, the Advanced IO Wizard provides GUI options to define the high level interface which are converted to XPHY Attributes. Please refer AM010 for more information on XPHY attributes.

For Advanced users, we defined a mechanism to tweak the attributes which are not visible in the GUI. The attributes can be overridden at nibble or bit level depending on their access through Tcl.

Table 1. XPHY Attributes
XPHY ATTRIBUTES	Syntax for BUS<<n>>_XPHY_ATTR	Default Values	Direct Attribute Access Through Tcl
CRSE_DLY_EN FALSE TRUE	CRSEDLYEN_<<value>>	FALSE	Nibble
CASCADE_<0-5> FALSE TRUE	CASCADE_<<value>>	FALSE	Bit
CONTINUOUS_DQS FALSE TRUE	CONTINUOUSDQS_<<value>>	FALSE	Nibble
DELAY_VALUE_<0-5> 0 to 625	DELAYVALUE_<<value>>	0	Bit
DIS_IDLY_VT_TRACK FALSE TRUE	DISIDLYVTTRACK_<<value>>	FALSE	Nibble
DIS_ODLY_VT_TRACK FALSE TRUE	DISODLYVTTRACK_<<value>>	FALSE	Nibble
DIS_QDLY_VT_TRACK FALSE TRUE	DISQDLYVTTRACK_<<value>>	FALSE	Nibble
DQS_MODE DDR41TCK DDR42TCK DDR3	DQSMODE_<<value>>	DDR41TCK	Nibble
EN_DYN_DLY_MODE FALSE TRUE	ENDYNDLYMODE_<<value>>	FALSE	Nibble
FAST_CK FALSE TRUE	FASTCK_<<value>>	FALSE	Nibble
FIFO_MODE_<0-5> ASYNC SYNC BYPASS	FIFOMODE_<<value>>	ASYNC	Bit
IBUF_DIS_SRC_<0-5> EXTERNAL INTERNAL	IBUFDISSRC_<<value>>	EXTERNAL	Bit
INV_RXCLK FALSE TRUE	INVRXCLK_<<value>>	FALSE	Nibble
LP4_DQS FALSE TRUE	LP4DQS_<<value>>	FALSE	Nibble
ODELAY_BYPASS_<0-5> FALSE TRUE	ODELAYBYPASS_<<value>>	FALSE	Bit
ODT_SRC_<0-5> FALSE TRUE	ODTSRC_<<value>>	FALSE	Bit
REFCLK_FREQUENCY Initialized to 1600	REFCLKFREQ_<<value>>	Initialized to 1600	Interface
RX_CLK_PHASE_N SHIFT0 SHIFT90	RXCLKPHASEN_<<value>>	SHIFT0	Bit
RX_CLK_PHASE_P SHIFT0 SHIFT90	RXCLKPHASEP_<<value>>	SHIFT0	Bit
RX_DATA_WIDTH 2 4 8	RXDATAWIDTH_<<value>>	8	Nibble
RX_GATING DISABLE ENABLE	RXGATING_<<value>>	DISABLE	Nibble
SELF_CALIBRATE DISABLE ENABLE	SELFCALIBRATE_<<value>>	DISABLE	Nibble
SERIAL_MODE FALSE TRUE	SERIALMODE_<<value>>	FALSE	Nibble
TBYTE_CTL0-5 T PHYWREN	TBYTECTL_<<value>>	T	Bit
TXRX_LOOPBACK_<0-5> FALSE TRUE	TXRXLOOPBACK_<<value>>	FALSE	Bit
TX_DATA_WIDTH 2 4 8	TXDATAWIDTH_<<value>>	8	Nibble
TX_GATING DISABLE ENABLE	TXGATING_<<value>>	DISABLE	Nibble
TX_INIT_<0-5> 0 1	TXINIT_<<value>>	0	Bit
PRIME_VAL 0 1	PRIMEVAL_<<value>>	0	Nibble
TX_OUTPUT_PHASE_90_<0-5> FALSE TRUE	TXOUTPUTPHASE90_<<value>>	FALSE	Bit
TX_OUTPUT_PHASE_90_TRI FALSE TRUE	TXOUTPUTPHASE90TRI_<<value>>	FALSE	Nibble

Examples of Tcl console inputs to change the XPHY attributes

set_property -dict [list CONFIG.BUS0_XPHY_ATTR {FIFOMODE_0_SYNC, FIFOMODE_1_SYNC}] [get_ips advanced_io_wizard_0]
For pin/bit level changes.
set_property -dict [list CONFIG.BUS0_XPHY_ATTR {FIFOMODE_0_SYNC, FIFOMODE_1_SYNC , FIFOMODE_BYPASS}] [get_ips advanced_io_wizard_0]
If you pass both the broadcast (nibble level) and bit/pin level attribute values, then the broadcast gets priority over bit/pin level values.
If a strobe is present, S0 is passed at bit/pin level as FIFOMODE_S0_SYNC and if write clock is present in case of BIDIR mode, W0 is passed as FIFOMODE_W0_SYNC from the Tcl console. After these values are passed, data pins always start from 0th position.
set_property -dict [list CONFIG.BUS0_XPHY_ATTR {FIFOMODE_S0_SYNC , FIFOMODE_0_SYNC , FIFOMODE_1_SYNC}] [get_ips advanced_io_wizard_0]

If you have one strobe and two single ended data pins enabled:

For differential pair, both P and N needs to be changed at bit/pin level.
Rule engine errors have a higher priority over the user input.
The advanced bit mode changes are applicable to both IP and example design.