This chapter contains information about the test bench provided in the Vivado® Design Suite. The test bench is a simple Verilog code to exercise the example design and the core. This test bench performs the following tasks:
- Generates input clock signals.
- Applies reset to the example design.
- Example design RX and TX interfaces are looped back. The waveform is shown for the TX/RX loopback for 1 pin.
- If RX and TX pattern matches, the test bench sends a message in Tcl console of Vivado® for successful test completion, as shown in the following figure. Otherwise, it waits for 1500 us and sends a test failure message.
Figure 1. Test Bench
