Advanced Tab - 1.0 English

The Advanced tab is shown in the following figure.

Figure 1. Advanced Tab

Optional Ports

XPLL CLKOUT1

Setting this enables the CLKOUT1 port of XPLL0 to be brought as the output port of the wrapper.

PLL_CLKOUT1_FREQ

Select the required frequency from this drop-down menu.

FIFO WRCLK OUT

Setting this exposes the fifo_wr_clk output port of the interface.

Note: Other XPLL outputs are provided by default. There is no need to enable them. For more information, see Port Descriptions.

REDUCE CONTROL SIGNALS

When enabled, a single set of control signals (fifo_wrclk, dly_rdy, phy_rdy, fifo_empty, and fifo_rden) of the XPHY nibble are presented to the user. It is an aggregation of the status signals from multiple nibbles.

ENABLE ALL PORTS OF XPHY

When enabled, all the control ports, RIU signals and other XPHY signals that a user needs is available at the top level of the wizard.

ENABLE DELAY CONTROL SIGNALS

When enabled, all XPHY ports related to delay control appear at the top level of the Wizard. The LD, CE, INC, CNTVALUEIN, CNTVALUEOUT, TX EN VTC, and RX EN VTC ports with respect to each bus are available to control delays on the IOs.

ENABLE VREF TUNING

When enabled, VREF tuning is on and the respective ports are exposed.

Enable Debug Ports

When enabled, all ILA related debug ports are exposed. The debug_bus port is exposed when this option is chosen. The debug bus can be used for debugging through ILA.

Enable ILA in Example Design

This option is available only if Enable Debug Ports is selected. Selecting Enable ILA in example design instantiates an ILA in the IP example design, which is useful for debug purposes.

Enable BLI logic

When enabled, the BLI registers between the fabric and XPHY can be used to help with timing closure.

Note: Enabling this parameter adds the latency of one clock cycle in the datapath. It is recommended to enable this parameter to meet timing.

Enable Simple RIU

When this parameter is enabled, only 1 RIU Interface appears at the top level of the wizard. All the RIU interfaces of the nibbles instantiated are mixed with the single RIU at the top. In this feature, riu_nibble_sel plays an important role in the read and write of RIU data. The width of the riu_nibble_sel port is equal to 9* NUM_BANKS. For example, if the single bank option is enabled, nine bits of riu_nibble correspond to each nibble of the bank. Bit0 corresponds to Nibble0, Bit1 to Nibble1, and so on. When more banks are enabled, Bit9 corresponds to Nibble0 of Bank1 and so on. The nibble_select bit must be held High and the signals must be driven on RIU signals.

You can also broadcast the write data onto all Nibbles by enabling all the bits in riu_nibble_sel bus.

I/O Standard Selection

Differential IO Std

Differential IO standards supported by the selected bank are shown here.

Single IO Std

Single-ended IO standards supported by the selected bank are shown here.

Note: The IO standard is limited to what XPIO banks allow.

DC Biasing

• DC bias values can be set for differential IO standards (DIFF_SSTL12, DIFF_POD12, LVDS15, DIFF_LVSTL_11, DIFF_LVSTL06_12). This option is applicable only for the input ports.

Number of Banks

Enable to select the number of banks to configure. The allowed values are 1, 2, and 3. The default value is 1. The port width of RIU and other control ports depends on this parameter. The maximum number of pins in the Pin Configuration tab is also restricted by this parameter.

Multi Banks are part of a Triplet

This option is enabled when the number of banks is greater than 1.

Power Saving

IOB Power Saving

Enable this option to get the power saving ports of IOBs at the top level for user control or internally controlled by XPHY.

IOB Power Control

Power control ports can be user driven or XPHY controlled, this option allows user to select one of them. When the User Controlled option is selected, the ibufdisable and dcitermdisable ports for each IO are available at IP level.

Note: For ES1 devices, IOB Power Control is always user controlled.

FIFO Mode Options

FIFO MODE enablement

Enable this option to enable the different FIFO modes supported by XPHY. You can enable the following FIFO modes:

• SYNC
• ASYNC
• BYPASS

FIFO Read Enable User Control

This option is enabled when the FIFO mode option is SYNC.