Bidirectional Mode Support - 1.0 English

Bidirectional feature is supported by the Wizard. There are 3 different BIDIR Modes that the Wizard supports.

Independent WrClk and RdClk

In this scenario, you have two separate pins each for WrClk and RdClk. Data I is bidirectional but the clocks are uni-directional and continuous. RdClk must follow the placement rules of the strobe and it must always be placed in Nibbleslice0. WrClk can be placed at any Nibbleslice.

Single Continuous Clock

Data and Clock associated with the data are bidirectional, and the clock associated with the data is always continuous.

Single Strobe

Data and clock associated with the data are bidirectional, and the clock associated with the data is not continuous. When an IO is configured as BIDIR, make sure that when using the bidirectional data path to tristate the buffer or gate the data paths to prevent data loss. The following must be enforced.

• You cannot use TRI_SELECT as serialized in an independent WrClk and RdClk mode in the following condition. If BIDIR and WrClk pins share same nibble and WrClk is not placed in NIbbleSlice 1 position. In this scenario we recommend to use TRISTATE to Combinatorial.
• When the BIDIR interface is ready to receive the data, assert PHY_RDEN (can keep high forever). FIFO_RDEN should follow the FIFO_EMPTY.
• When the BIDIR interface is ready to write data, assert PHY_WREN to write data. De-assert PHY_WREN when the write is complete.
  Note: For alignment of the data across the Nibble, bitslip pattern must be enabled with a fixed training pattern. Pattern can be mentioned in IP GUI.
• RIU interface must be enabled when using BIDIR data to enable proper turnaround from between TX and RX without any data loss.
• Turn around process when TRI_STATE is serialized
  • After the write is complete, de-assert PHY_WREN.
  • Issue BS_RESET_TRI, BS_RESET and CLR_GATE before asserting PHY_RDEN to bring pointers to a known position.
  • Use the RIU register BS_RESET_CTRL (RIU_ADDR 0x03) with RIU_WR_DATA = 0x0007 for eight RIU clock periods before de-asserting the resets with RIU_WR_DATA = 0x0000.
  • No need to assert clear gate or BS_RESET again after PHY_RDEN de-assertion.
  • FIFO_RDEN should follow FIFO_EMPTY. Bitslip is required in the beginning of read across bank.

Bidirectional state machine (SM) is optional from IP (EN_BIDIR_SM), when this option is enabled, state machine is included to switch the core and example design behavior from TX to RX or vice versa. When the SM is in progress, no rd/wr action is performed and all the signals (phy_rd_en and phy_wr_en) will be deasserted. During this, SM is in active state. Issue BS_RESET_TRI, BS_RESET and CLR_GATE before asserting PHY_RDEN to bring pointers to known position. Use the RIU register BS_RESET_CTRL (RIU_ADDR 0x03) with RIU_WR_DATA = 0x0007 for eight RIU clock periods before deasserting the resets with RIU_WR_DATA = 0x0000. No need to assert clear gate or BS_RESET again after PHY_RDEN deassertion. The SM will give done signal which will be used internally to switch the roles from TX to RX or vice versa. If EN_BIDIR_SM is not selected, then you need to add your own custom BIDIR state machine to make the switch between roles of TX/RX. In the example design, the roles are switched with the counter logic without riu SM in the case of EN_BIDIR_SM=0.