MODULE_CTRL Register (0x04) - MODULE_CTRL Register (0x04) - 2.0 English - PG290

SMPTE UHD-SDI Receiver Subsystem LogiCORE IP Product Guide (PG290)
Document_ID
PG290
Release_Date
2026-07-22
Version
2.0 English

This register provides control of the SMPTE UHD-SDI RX IP core and core functional modes.

Table 1. MODULE_CTRL Register Bit Mapping
Bits Name Access Default Value Description
31:19 Reserved RO 0 Reserved
18:16 RX_FORCED_MODE R/W 0 RX forced mode
  • 3’b000: HD mode
  • 3’b001: SD mode
  • 3’b010: 3G mode
  • 3’b100: 6G mode
  • 3’b101: 12G mode with 11.88 Gb/s line rate
  • 3’b110: 12G mode with 11.88/1.001 Gb/s line rate
15:14 BPP value R/W 0 The subsystem uses this register only if the Enable Dynamic BPP Change option is enabled
  • 2'b00: System is configured to a 8 bit system
  • 2'b01: System is configured to a 10 bit system
  • 2'b10: System is configured to a 12 bit system
13:8 RX_MODE_EN R/W 0 RX mode enable
  • Bit8: Enable HD-SDI mode
  • Bit9: Enable SD-SDI mode
  • Bit10: Enable 3G-SDI mode
  • Bit11: Enable 6G-SDI mode
  • Bit12: Enable 12G-SDI 11.88 Gb/s mode
  • Bit13: Enable 12G-SDI 11.88/1.001 Gb/s mode
7:6 Reserved RO 2’b01 Reserved
5 RX_MODE_DET_EN R/W 0 RX mode detection enable
4 RX_FRM_EN R/W 0 RX frame enable
3:0 Reserved RO 0 Reserved