Register Space - 2.0 English

The Audio Pattern Generator (PatGen) IP register space is shown in the following table.

Table 1. Audio Pattern Generator Register Space
Reg Offset	Name	Reg Description
0x00	Control Register	Control register
0x04	Fs Multiplier	Register to specify Fs multiplier
0x08	Patgen Configuration	PatGen configuration such as channels, pattern, sampling and data width
0x0C	Silence time register	Specify any silence time to create a beep pattern
0x10-0x24	Channel Status Bits	Specify the 192 bits channel status
0x28-0x3C	User Status bits	Specify the 192 bits user bits
0x40	Validity register	Set the validity bit for samples
0x44	Checker Status	To check the checker result
0x48	Valid sample counter	Counts the number valid samples that were checked
0x4C	Number of samples missed counter	Counts number data mismatches that occurred
0x50	Data received	Incoming data sample register
0x54	Previous data	Previous sampled data register

The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal, and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a Write, both the AXI Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together.

Core Control Register (0x00)

This register is used to control the APG and change its behavior to either generate audio traffic or put it in by-pass mode. The APG, by default, is in bypass mode. When APG is to be started, by-pass should be disabled.

Table 2. Core Control Register
Name	Default Value	Access	Description
Bypass enable	0x1	RW	[31] This bit is used to enable the bypass mode. In this mode the APG is bypassed and whatever that comes on input AXIS is forwarded to output AXIS interface. This bit has a higher priority than bit [0].
Reserved			[30:2]
Start Checker	0x0	RW	[1] This bit enables the checker. Checker keeps checking the AXIS data received from the S_AXIS ports.
Enable APG	0x0	RW	[0] Set this bit to start the APG or put in generate mode. This should be enabled after all other config registers have been written.

Note: All of the following registers, except 0x40, can be written only when the ‘Enable APG’ bit of Core Control Register is 0. All of the following registers have to be programmed first before starting the APG.

Fs Multiplier Register (0x04)

Program this register to specify the multiplier value of the aud_clk.

Table 3. Fs Multiplier Register
Name	Default Value	Access	Description
RSVD			[31:16]
Multi Value	0x180	RW	[15:0] Specify the multiplier value of the aud_clk. For example, for Fs = 48 kHz, the supplied aud_clk is 18.432 MHz, then this register should be programmed with a value of 384. i.e. 48 kHz * 384 = 18.432 MHz

APG Config Register (0x08)

This registers provides capability to enable/disable the core.

Table 4. APG Config Register
Name	Default Value	Access	Description
Channel count	0x2	RW	[31:24] Set number of audio channels. Valid values are 2, 4, 6 and 8.
Data width	0x4	RW	[23:16] Specify the width of audio data samples. Valid values are: 001 – 16 bit audio samples 010 – 20 bit audio samples 100 – 24 bit audio samples
Sampling Frequency	0x2	RW	[15:8] Specify the sampling rate of the audio samples. Valid values are: 000 – 32 kHz 001 – 44.1 kHz 010 – 48 kHz
Pattern	0x0	R/W	[7:0] Select from internal patterns. Valid values are: 000 – 1 kHz sine wave 001 – 2 kHz sine wave 010 – 1 kHz sine wave on left, 2 kHz sine wave on right channel 111 – Incremental pattern

APG Silence Register (0x0C)

This register is used to insert a silence time. This can be programmed to create a beep pattern of either 1 kHz or 2 kHz sine wave.

Table 5. APG Silence Register
Name	Default Value	Access	Description
Reserved	0		[31:16]
Silence interval	0	RW	[15:0] Specify a value to insert periodic silence. The silence time is twice the value that is programmed here. Silence time = 2valueaud_clk Period A value of 0 means no silence.

Channel Status Register (0x10-0x24)

Specify the 192 bits of Channels Status information using these 6 registers. Each register is to be programmed with 32 bits of data in order of LSB to MSB.

Table 6. Channel Status Register
Name	Default Value	Access	Description
Channel Status	0	RW	[31:0] Specify the 32-bit information.

User Info Register (0x28-0x3C)

Specify the 192 bits of User information using these 6 registers. Each register is to be programmed with 32 bits of data in order of LSB to MSB.

Table 7. User Info Register
Name	Default Value	Access	Description
User info	0	RW	[31:0] Specify the 32-bit information.

Validity Control (0x40)

This bit allows the user to set the validity bit in the Audio sample.

Table 8. Validity Control
Name	Default Value	Access	Description
Reserved	0		[31:1]
Validity	0x0	R/W	[0] This bit can be used to set the validity bit inside the audio sample frame. Receivers typically ignore the samples, which have the validity bit set to ‘1’.

Checker Status (0x44)

This register allows the user to check the status of the checker function

Table 9. Checker Status
Name	Default Value	Access	Description
Checker started	0x0	R	[31] 1 – when at least one valid sample was detected
Reserved	0x0		[30:8]
Data mismatch channel	0x0	R	[7:5] Channel ID where the first data mismatch occurred
ID error	0x0	R	[4] Error due to wrong ID pattern
Parity	0x0	R	[3] Error in parity bit
Preamble	0x0	R	[2] Error in preamble bits
Data mismatch error	0x0	R	[1] Error in incremental pattern
Checker status (Channel0_status)	0x0	R	[0] When start checker is enabled, the checker keeps checking for an incremental pattern. If there is a mismatch, this bit goes High.

Valid Sample Counter (0x48)

Table 10. Valid Sample Counter
Name	Default Value	Access	Description
User info	0	RW	[31:0] Specify the 32 bit information.

Number of Samples Missed Counter (0x4C)

Table 11. Number of Samples Missed Counter
Name	Default Value	Access	Description
No_of_samples_missed	0x0	R	[31:0] Counter value indicating number of missed samples in case of an error.

Data Received (0x50)

This register gives the information of the incoming data sample when the first data mismatch error occurred.

Table 12. Data Received
Name	Default Value	Access	Description
Reserved			[31:24]
Incoming data	0x0	R	[23:0] Data received on s_aud_tdata when the error occurred.

Previous Data (0x54)

This register stores the previous sampled data available when the data mismatch error occurred.

Table 13. Previous Data
Name	Default Value	Access	Description
Reserved			[31:24]
Sampled data	0x0	R	[23:0] Previous sampled data when error occurred. Current data should be sampled data + 1

A data mismatch error occurs when incoming data is not equal to the previously sampled data + 1.