This register captures the error and status information for the IP core.
| Bits | Name | Access 1 | Default Value | Description |
|---|---|---|---|---|
| 31:11 | Reserved | RO | 0 | Reserved |
| 10 | UNDERFLOW_INTR | R/W1C | 0 | Video in to AXI4-Stream core underflow indication. This bit is available only in AXI4-Stream is selected as Video Interface. |
| 9 | OVERFLOW_INTR | R/W1C | 0 | Video in to AXI4-Stream core overflow indication. This bit is available only in AXI4-Stream is selected as Video Interface. |
| 8:3 | Reserved | RO | 0 | Reserved |
| 2 | VSYNC_VALID_INTR | R/W1C | 0 | Asserted when Video sync has been detected at the start of each frame. |
| 1 | VIDEO_UNLOCK_INTR | R/W1C | 0 | Asserted when incoming video pattern is unlocked |
| 0 | VIDEO_LOCK_INTR | R/W1C | 0 |
Asserted when incoming video pattern is locked and ST352 Valid bit of Data Stream1 (RX_ST352_VLD_DS1 field) is asserted. |
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