This register is used to control the APG and change its behavior to either generate audio traffic or put it in by-pass mode. The APG, by default, is in bypass mode. When APG is to be started, by-pass should be disabled.
|
Name |
Default
|
Access |
Description |
|---|---|---|---|
|
Bypass enable |
0x1 |
RW |
[31] This bit is used to enable the bypass mode. In this mode the APG is bypassed and whatever that comes on input AXIS is forwarded to output AXIS interface. This bit has a higher priority than bit [0]. |
|
Reserved |
|
|
[30:2] |
|
Start Checker |
0x0 |
RW |
[1] This bit enables the checker. Checker keeps checking the AXIS data received from the S_AXIS ports. |
|
Enable APG |
0x0 |
RW |
[0] Set this bit to start the APG or put in generate mode. This should be enabled after all other config registers have been written. |
Note: All of the following registers, except 0x40, can be written only when the ‘Enable APG’ bit of Core Control Register is 0. All of the following registers have to be programmed first before starting the APG.