M_AXIS_CTRL_SB_RX Interface Ports - 2.0 English

SMPTE UHD-SDI Receiver Subsystem LogiCORE IP Product Guide (PG290)

Document ID
PG290
Release Date
2024-06-19
Version
2.0 English
Table 1. M_AXIS_CTRL_SB_RX Port Descriptions
Signal I/O Description
M_AXIS_CTRL_SB_RX__tready I Core Ready
M_AXIS_CTRL_SB_RX_tvalid O Data valid
M_AXIS_CTRL_SB_RX_tdata[31:0] O

Sideband signal information from transceiver block

bit 2:0: rx_mode

bit 3: rx_mode_locked

bit 4: rx_level_b_3g

bit 5: rx_ce

bit 31–6: unused