The SDI RX to Video Bridge AMD LogiCORE™ IP core is designed to interface between native SDI and native video. The input is an SDI virtual interface that has one to eight data streams with embedded synchronization. The output is video data with explicit synchronization signals. This core extracts synchronization signals, reformats the video data, and provides clock enables.
The core extracts embedded synchronization signals
from the SDI data stream.
Important: It supports SD-SDI,
HD-SDI, 3G-SDI Level A, 3G-SDI Level B, 6G-SDI and 12G-SDI with YCbCr data format at 10 bits
and 12 bits per component. 10 bits per component data is not supported when configured in 12
bit mode.
For 3G-SDI Level B, it automatically reorders two lines of parallel data to
sequential lines of video data out. It supports both interlaced and progressive line
standards.