Example Design - 2.0 English

SMPTE UHD-SDI Receiver Subsystem LogiCORE IP Product Guide (PG290)

Document ID
PG290
Release Date
2024-06-19
Version
2.0 English

This chapter contains information about the example design provided in the AMD Vivado™ Design Suite.

Table 1. Example Design Hardware Requirements
Topology Required Hardware Processor UHD-SDI GT Configuration GT Type GT Data Width BPC
      TXPLL RXPLL      

(Video)

Pass-Through

  • ZCU106
  • 2 HD-BNC to BNC cables
  • SDI source and sink devices
A53 QPLL1 QPLL0 GTHE4 40-bit 10

Audio-Video

Pass-Through

SDI Audio Pass-Through

  • ZCU106
  • 2 HD-BNC to BNC cables
  • SDI source and sink devices

SDI Audio Playback to AES

  • ZCU106
  • 3 HD-BNC to BNC cables
  • SDI source and sink devices
  • AES Sink

AES capture to SDI TX

  • ZCU106
  • 3 HD-BNC to BNC cables
  • SDI source and sink devices
  • AES source
A53 QPLL1 QPLL0 GTHE4 40-bit 10
Audio-Video Loopback
  • KCU116
  • Fidus TB-FMCH-12GSDI SDI FMC
  • 1 HD-BNC to HD-BNC cable
MicroBlaze™ CPLL

QPLL0(1)/

QPLL1(2)

GTYE4 40-bit 10
RX-Only
  • ZCU106
  • 1 HD-BNC to BNC cable
  • Sink device
A53 QPLL1 QPLL0 GTHE4 40-bit 10

Versal Audio-Video

Pass-Through

SDI Versal Video Pass-Through

  • VCK190
  • Fidus TB-FMCH-12GSDI SDI FMC
  • 2 HD-BNC to BNC cables
  • SDI source and sink devices
A72 RPLL LCPLL GTYES 40-bit 10