RX_EDH_STS Register (0x4C) - RX_EDH_STS Register (0x4C) - 2.0 English - PG290

SMPTE UHD-SDI Receiver Subsystem LogiCORE IP Product Guide (PG290)

Document ID: PG290
Release Date: 2025-11-26
Version: 2.0 English

Table 1. RX_EDH_STS Register Bit Mapping
Bits	Name	Access	Default Value	Description
31:23	Reserved	RO	0	Reserved
22:19	RX_EDH_PKT_FLAGS	RO	0	This four error flags related to the most recently received EDH packet. See SD-SDI EDH Error Detection in the SMPTE UHD-SDI LogiCORE IP Product Guide (PG205) for details on the encoding of the bits.
18:14	RX_EDH_ANC_FLAGS	RO	0	The ancillary error flag bits from the most recently received EDH packet. See SD-SDI EDH Error Detection in the SMPTE UHD-SDI LogiCORE IP Product Guide (PG205) for details on the encoding of the bits.
13:9	RX_EDH_FF_FLAGS	RO	0	The full frame error flag bits from the most recently received EDH packet. See SD-SDI EDH Error Detection in the SMPTE UHD-SDI LogiCORE IP Product Guide (PG205) for details on the encoding of the bits.
8:4	RX_EDH_AP_FLAGS	RO	0	The active picture error flag bits from the most recently received EDH packet. See SD-SDI EDH Error Detection in the SMPTE UHD-SDI LogiCORE IP Product Guide (PG205) for details on the encoding of the bits.
3	Reserved	RO	0	Reserved
2	RX_EDH_ANC	RO	0	This output is asserted High when an ancillary data packet checksum error is detected.
1	RX_EDH_FF	RO	0	This bit is asserted High when the full field CRC calculated for the previous field does not match the FF CRC value in the EDH packet.
0	RX_EDH_AP	RO	0	This bit is asserted High when the active picture CRC calculated for the previous field does not match the AP CRC value in the EDH packet.