| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Subsystem Specifics | |
| Supported Device Family 1 |
AMD UltraScale+™ (GTHE4, GTYE4) AMD Versal™ Adaptive SoC (GTYE5, GTYP) AMD Zynq™ UltraScale+™ MPSoC (GTHE4, GTYE4) Zynq UltraScale+ RFSoC |
| Supported User Interfaces | AXI4-Lite, AXI4-Stream, native video, and native SDI |
| Resources | Performance and Resource Utilization web page |
| Provided with Subsystem | |
| Design Files | Hierarchical subsystem packaged with SMPTE UHD-SDI RX core and other IP cores |
| Example Design | AMD Vivado™ IP integrator |
| Test Bench | N/A |
| Constraints File | IP cores delivered with XDC files |
| Simulation Model | N/A |
| Supported S/W Driver 2 | Standalone and Linux |
| Tested Design Flows 3 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 68766 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
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