Clocking - 2.0 English

SMPTE UHD-SDI Receiver Subsystem LogiCORE IP Product Guide (PG290)

Document ID
PG290
Release Date
2024-06-19
Version
2.0 English

There are three possible clock inputs available:

s_axi_aclk
AXI4-Lite control interface clock
aud_aclk
Reference audio MCLK. This is typically a multiple of Fs (for example, Fs*384).
m_axis_aud_aclk
AXIS streaming interface clock