S_AXIS_STS_SB_RX Interface Ports - 2.0 English

SMPTE UHD-SDI Receiver Subsystem LogiCORE IP Product Guide (PG290)

Document ID
PG290
Release Date
2024-06-19
Version
2.0 English
Table 1. S_AXIS_STS_SB_RX Interface Port Descriptions
Signal I/O Description
S_AXIS_STS_SB_RX_tready O Core ready
S_AXIS_STS_SB_RX_tvalid I Data valid
S_AXIS_STS_SB_RX_tdata[31:0] I

Sideband signal information from transceiver block

bit 0: rx_change_done—Indicates that SDI line rate is successful

bit 2: gtrxresetdone

bit 3: rx_m (Integer = 0, Fractional = 1)

bit 8: rx_fabric_rst—SMPTE UHD-SDI RX IP is reset when this bit set to 1

All other bits are not used.