Note: Refer to the Versal Adaptive SoC
Lounge support forum at Support for details about clock implementation and
other tool tweaks.
- Make sure QPLL is getting reset before starting the IP.
- Monitor the QPLL LOCK signal.
- Verify that QPLL input clock frequency is of expected value.
- It is mandatory to reset the QPLL if clock input to QPLL is stopped or unstable.
- See AR 57738 for debugging GT reference clock issues.
- Make sure to use QPLL default settings from latest GT Wizard IP core based on target device.
- Check the voltage rails on the transceivers. See AR 57737 for more information.
- Measure
RXOUTCLKis of expected frequency. - Make sure
RXOUTCLKof the transceiver is the clock drivingrx_usrclk,RXUSRCLK, andRXUSRCLK2. - Monitor
RXBUFFSTATUS[2:0] for overflow and underflow errors.