Ensure that all the timing constraints for the core were properly incorporated from the example design and that all constraints were met during implementation.
- Check that MMCM lock and PLL lock signal(s) are asserted.
- Verify the IO pin planning and XDC constraints.
- Follow the recommended reset sequence.
- Verify all clocks are connected and are with expected frequencies.
- Enable AXI4-Lite based register interface to get core status and control.
- Make sure serial line trace lengths are equal.
- Verify the FMC_VADJ voltage to 1.8V in case of FMC card usage.
The following figure shows the steps to perform a hardware debug.
Figure 1. Hardware Debugging
