S_AXIS_RX Interface Ports - 2.0 English - PG290

SMPTE UHD-SDI Receiver Subsystem LogiCORE IP Product Guide (PG290)

Document ID
PG290
Release Date
2024-12-11
Version
2.0 English
Table 1. S_AXIS_RX Port Descriptions
Signal I/O Description
sdi_rx_clk I SMPTE SDI RX core clock
sdi_rx_rst I Active-High reset
S_AXIS_RX_tready O SMPTE SDI RX core ready
S_AXIS_RX_tvalid I Data valid
S_AXIS_RX_tdata[n-1:0] I

Parallel data received from transceiver.

n varies with SDI standard selection:

n=40 for 6G-SDI and 12G-SDI

n=20 for 3G-SDI

S_AXIS_RX_tuser[31:0] I TUSER Information. Not used.